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mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet 1. features and benefits ? 3 - phase bldc gate driver ? level shifting between mcu pwm outputs and 3 external half - bridges ? compatible with 3.3v - 5v microcontrollers ? supporting different driver strength ? mlx83203: 1.00a gate drivers ? mlx83202: 0.33a gate drivers ? supported supply voltage range ? absolute maximum rating: 45v ? operating range: 4.5v - 28v ? 12v - 28v battery systems ? automotive qualified for 12v ? sleep mode with current <30a ? two charge pump configuratio n modes for ? low voltage operation ? reverse polarity n - fet protection ? high - side gate drivers with bootstrap circuits ? integrated 12v voltage regulator ? supports 6x 350nc n - fets at 20khz pwm ? supports 100% pwm operation ? integrated current sense amplifier ? low off set and low offset drift ? fast settling time < 1s ? programmable gain: 8x - 48x ? extensive diagnostics ? under/over voltage detection ? over temperature warning ? programmable v ds monitoring ? v gs monitoring ? serial, pwm diagnostics interface ? configurable diagnostics ? full diagnostic feedback ? customer configurable eeprom ? driver configuration ? diagnostics configuration ? small package ? 32 - pin qfn - ep, aec - q100 grade 1 qualification (t j =150?c) ? wettable flanks 2. application examples ? automotive 12v bldc applications ? water pump / oil pump / fuel pump ? engine cooling fan ? hvac blower / compressor ? industrial bldc motor drivers up to 28v ? pumps ? fans ? blowers / c ompressors 3. ordering information product temperature package option code packing form mlx83203 k ( - 40c to 125c) lw (qfn32 - ep 5x5mm wettable flanks) dba - 000 re (reel) mlx83202 k ( - 40c to 125c) lw (qfn32 - ep 5x5mm wettable flanks) dba - 000 re (reel) ordering example: mlx83203klw - dba - 000 - re.
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 2 of 42 r evision 5. 1 C december 1 3 , 2016 4. functional diagram figure 4 - 1 typical a pplication diagram figure 4 - 2 alternative application diagram with reverse polarity n - fet m l x 8 3 2 0 3 - 2 b l d c p r e - d r i v e r m a d c m c u l s g a t e d r i v e r s i / o i / o v d d s u p p l y d r i v e r l o g i c s h o o t t h r o u g h p r o t e c t i o n d e a d t i m e c u r r e n t s e n s e a m p l i f i e r 1 2 v r e g u l a t o r - d r i v e r s u p p l y e n f e t b 1 - 3 f e t t 1 - 3 g a t e t 1 g a t e t 2 g a t e t 3 g a t e b 1 g a t e b 2 g a t e b 3 p h a s e 1 p h a s e 2 p h a s e 3 c p 1 c p 2 c p 3 v b a t f v r e g v s u p d g n d a g n d v b a t e e p r o m c u s t o m i n t e r f a c e i b p i b m d i a g n o s t i c s e r r o r o u t p u t v d d i n t e r n a l s u p p l y i c o m v r e f i s e n s e 3 . 3 v - 5 v s u p p l y h s g a t e d r i v e r s p w m c h a r g e p u m p c p v b o o s t m l x 8 3 2 0 3 - 2 b l d c p r e - d r i v e r m a d c m c u l s g a t e d r i v e r s i / o i / o v d d s u p p l y d r i v e r l o g i c s h o o t t h r o u g h p r o t e c t i o n d e a d t i m e c u r r e n t s e n s e a m p l i f i e r 1 2 v r e g u l a t o r - d r i v e r s u p p l y e n f e t b 1 - 3 f e t t 1 - 3 g a t e t 1 g a t e t 2 g a t e t 3 g a t e b 1 g a t e b 2 g a t e b 3 p h a s e 1 p h a s e 2 p h a s e 3 c p 1 c p 2 c p 3 v b a t f v r e g v s u p d g n d a g n d v b a t e e p r o m c u s t o m i n t e r f a c e i b p i b m d i a g n o s t i c s e r r o r o u t p u t v d d i n t e r n a l s u p p l y i c o m v r e f i s e n s e 3 . 3 v - 5 v s u p p l y h s g a t e d r i v e r s p w m c h a r g e p u m p c p v b o o s t v d d
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 3 of 42 r evision 5. 1 C december 1 3 , 2016 5. general description the mlx83203 - 2 is a three phase pre - driver (also called bridge or gate driver) ic with integrated current sense amplifier. this device is used to drive brushless dc motors in combination with a microcontroller and six discrete power n - fets. for the high power applications the mlx83203 provides powerful gate drivers of 1a typical. the mlx83202 has reduced gate drive strength of 300ma and targets mid power applications. both devices are able to control six external n - fets in the supply range from 4.5v to 28v, by means of the integrated charge pump. the high side gate drivers are supplied via bootstrap circuits. the trickle charge pump allows 100% pwm operation despite the use of bootstrap capacitors. the bootstrap voltage regulator is optimized for gate charges up to 350nc per fet at 20 khz pwm. the device comprises various monitoring and protection functions, including under voltage and over voltage detection at multiple inte rnal voltage nodes, over temperature detection, drain - source and gate - source voltage monitoring of the external n - fets. in case of fault detection, the icom diagnostics interface will inform the microcontroller with a pwm signal, whose duty cycle indicates the nature of the error. an integrated fast, high - bandwidth, low offset current sense amplifier allows for precise torque control, with programmable gain selection. the mlx83203 - 2 provides an eeprom for configurability, avoiding the need for a high pin - c ount package. the configuration allows the customer to optimize the pre - drivers operation for different applications.
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 4 of 42 r evision 5. 1 C december 1 3 , 2016 6. contents 1. features and benefits ................................ ................................ ................................ ............................ 1 2. application examples ................................ ................................ ................................ ............................. 1 3. ord ering information ................................ ................................ ................................ ............................ 1 4. functional diagram ................................ ................................ ................................ ............................... 2 5. general description ................................ ................................ ................................ ............................... 3 6. contents ................................ ................................ ................................ ................................ ................ 4 7. pin configuration & definition ................................ ................................ ................................ ............... 5 7.1. pin configuration ................................ ................................ ................................ ................................ 5 7.2. pin definition ................................ ................................ ................................ ................................ ....... 5 8. absolute maximum ratings ................................ ................................ ................................ ................... 7 9. operating range ................................ ................................ ................................ ................................ .... 7 10. general electrical specifications ................................ ................................ ................................ .......... 8 10.1. mlx83203 typical performance graphs ................................ ................................ ....................... 15 10.2. mlx83202 typical performance graphs ................................ ................................ ....................... 16 11. block diagram ................................ ................................ ................................ ................................ .... 17 12. functional description ................................ ................................ ................................ ....................... 18 12.1. supply system ................................ ................................ ................................ ................................ . 18 12.2. gate drivers ................................ ................................ ................................ ................................ .... 23 12.3. integrated current sense amplifier ................................ ................................ ............................... 24 12.4. protection and diagnostic functions ................................ ................................ ............................. 25 12.5. eeprom configuration ................................ ................................ ................................ ................... 30 13 . esd protection ................................ ................................ ................................ ................................ ... 37 14. package information ................................ ................................ ................................ .......................... 38 14.1. package marking ................................ ................................ ................................ ............................. 38 14.2. package data ................................ ................................ ................................ ................................ ... 38 15. standard information regarding manufacturability of melexis products with different soldering processes ................................ ................................ ................................ ................................ ............ 39 16. esd precautions ................................ ................................ ................................ ................................ . 39 17. revision history ................................ ................................ ................................ ................................ . 40 18. disclaimer ................................ ................................ ................................ ................................ .......... 42
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 5 of 42 r evision 5. 1 C december 1 3 , 2016 7. pin configuration & definition 7.1. pin configuration figure 7 - 1 pin configuration 7.2. pin definition pin # name description 1 ibm current sense amplifier negative input 2 ibp current sense amplifier positive input 3 isense current sense amplifier output 4 fetb1 low - side fet1 pwm control input (active low) miso output for spi 5 fetb2 low - side fet2 pwm control input (active low) clk input for spi 6 fetb3 low - side fet3 pwm control input (active low) mosi input for spi 7 icom bidirectional, serial diagnostics interface csb input for spi 8 en enable input for gate driver outputs (active high) 9 phase2 motor phase 2 i b m i b p i s e n s e f e t b 1 f e t b 2 f e t b 3 i c o m e n 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 p h a s e 2 g a t e t 2 c p 2 p h a s e 1 g a t e t 1 c p 1 p h a s e 3 g a t e t 3 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 v s u p v b a t f a g n d f e t t 2 f e t t 1 f e t t 3 v d d v r e f 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 c p 3 v b o o s t v r e g g a t e b 2 g a t e b 3 g a t e b 1 d g n d c p 1 2 3 4 5 6 7 8
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 6 of 42 r evision 5. 1 C december 1 3 , 2016 10 gatet2 high - side fet2 gate driver output 11 cp2 high - side fet2 bootstrap capacitor 12 phase1 motor phase 1 13 gatet1 high - side fet1 gate driver output 14 cp1 high - side fet1 bootstrap capacitor 15 phase3 motor phase 3 16 gatet3 high - side fet3 gate driver output 17 cp3 high - side fet3 bootstrap capacitor 18 vboost charge pump boosted supply output 19 vreg driver supply output for bootstrap capacitors 20 gateb2 low - side fet2 gate driver output 21 gateb3 low - side fet3 gate driver output 22 gateb1 low - side fet1 gate driver output 23 dgnd driver ground 24 cp charge pump floating capacitor 25 vsup power supply input (battery input) 26 vbatf battery voltage connection for vds - monitoring 27 agnd analog ground 28 fett2 high - side fet2 pwm control input (active high) 29 fett1 high - side fet1 pwm control input (active high) 30 fett3 high - side fet3 pwm control input (active high) 31 vdd digital supply for ios and current sense amplifier 32 vref current sense amplifier reference input 33 pad exposed pad table 7 - 1 pin definition
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 7 of 42 r evision 5. 1 C december 1 3 , 2016 8. absolute maximum ratings parameter symbol min typ max unit condition power supply voltage v vsup , v batf - 0.3 - 45 v t < 500ms (during load dump) power supply voltage v vsup , v batf - 0.3 - 28 v permanent (functional) negative input current i vsup - 15 - - ma negative input current i vbatf - 10 - - ma defines with max. reverse polarity voltage the r vbatf digital supply voltage v vdd - 0.3 - 5.5 v analog input voltage v vref, v ibm ,v ibp - 0.3 - v dd +0.3 v analog output voltage v isense - 0.3 - v dd +0.3 v digital input voltage v fetbx , v fettx , v en - 0.3 - v dd +0.3 v digital input current - 10 - 10 ma digital output voltage v icom - 0.3 - v dd +0.3 v output voltage v gatebx, v reg - 0.3 - 17 v output voltage v gatetx - 0.3 - v reg +35 v input voltage on cpx pins v cpx - 0.3 - v reg +35 v input voltage on phasex pins v phasex - 0.7 - 45 v maximum latch - up free current at any pin i latch - 100 - 100 ma according to jedec jesd78, aec - q100 - 004 esd capability esd - 2 - +2 kv human body model storage temperature t stg - 55 - 150 ? c junction temperature t j - 40 - 150 ? c thermal resistance soic - 16 r th - ja - 37 - k/w in free air on multilayer pcb (jedec 1s2p) thermal resistance soic - 16 r th - jc - 10 - k/w referring center of exposed pad table 8 - 1 absolute maximum ratings exceeding the absolute maximum ratings may cause permanent damage. exposure to absolute maximum - rated conditions for extended periods may af fect device reliability. 9. operating range parameter symbol min typ max unit condition power supply voltage range v vsup 4.5 - 28 v full functionality digital supply voltage range v vdd 3 - 5.5 v cp discharged, power fets off ambient temperature t a - 40 - 125 ? c junction temperature t j - 40 - 150 ? c table 9 - 1 operating range
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 8 of 42 r evision 5. 1 C december 1 3 , 2016 10. general electrical specification s parameter symbol condition min. typ. max. unit power supply vsup no.1 supply voltage range v sup ? functional 7 - 18 v no.2 supply voltage extended range low v sup_erl ? functional w. decreased gate drive voltage 4.5 - 7 v no.3 supply voltage extended range high v sup_erh 18 - 28 v no.4 quiescent current from v sup i sup_sleep ? v dd = low - - 30 a no.5 operating current from v sup i sup_int ? pre - driver operation 25khz pwm, no load - - 5 ma no.6 supply over voltage high v sup_ovh ? warning on icom - - 35 v no.7 supply over voltage low v sup_ovl ? icom released 30 - - v no.8 supply over voltage hysteresis v sup_ovhy 0.4 - 1 v no.9 supply over voltage debounce time v sup_ov_deb - - 2 s no.10 supply under voltage high v sup_uvh ? icom released - - 6 v no.11 supply under voltage low v sup_uvl ? warning on icom 5 - - v no.12 supply under voltage hysteresis v sup_uvhy 0.2 - 0.5 v no.13 supply under voltage debounce time v sup_uv_deb - - 10 s no.14 power on reset level v por ? reset released on rising edge v sup when v dd = high 2.6 - 4.5 v vvbatf no.15 l eakage from v batf to gnd r vbatf_leak ? pre - driver not in sleep - - 30 a temperature warning no.16 over temperature high ovt h ? warning on icom - 185 - ? c no.17 over temperature low ovt l ? icom released - 168 - ? c on - chip oscillator no.18 oscillator frequency f osc ? internal oscillator 6.8 8 9.2 mhz
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 9 of 42 r evision 5. 1 C december 1 3 , 2016 charge pump cp, vboost no.19 output slew rate v cp - 100 - v/s no.20 charge pump frequency f cp 170 200 230 khz no.21 reverse polarity n - fet gate - source voltage (v boost - v sup ) v gs_rpfet ? cp mode 1 ? v sup > 7v ? i reg < 20ma 5 12 13 v no.22 resistive load from v boost to gnd r boost_leak ? r typ at room temperature ? r min at 150 ? j ? (excl. r vreg_leak ) 6 8 - mohm no.23 v boost under voltage high v boost_uvh icom released ? cp mode 0 (v boost) ? cp mode 1 (v boost - v sup ) 6.1 - 7.2 v no.24 v boost under voltage low v boost_uvl warning on icom ? cp mode 0 (v boost) ? cp mode 1 (v boost - v sup ) 5.6 - 6.7 v no.25 v boost discharge stop v boost_disst op ? cp mode 1 (v boost - v sup ) ? d ischarge activated by v sup_ov and topped by v boost_dis_stop v sup - 0.2 - v sup +0.8 v no.26 v boost discharge current i boost_dis ? cp mode 1 (v boost - v sup ) ? f rom v boost to dgnd 25 - 90 ma
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 10 of 42 r evision 5. 1 C december 1 3 , 2016 driver supply vreg no.27 load current on v reg i reg_cpmode0 ? v reg > 11v ? cp mode 0 , en_cp = 1 - - 40 ma i reg_cpmode1 ? v reg > 11v ? cp mode 1 , en_cp = 1 - - 20 ma no.28 output voltage v reg v reg ? cp mode 0 , en_cp = 1 ? v sup > 8v ? i reg < 40ma 11 12 13 v ? cp mode 0 , en_cp = 1 ? 7v< v sup < 8v ? i reg < 40ma 10 - 13 v ? cp mode 1 , en_cp = 1 ? i reg < 20ma 11 12 13 v no.29 internal resistive load from v reg to gnd r vreg_leak ? r typ at room temperature ? r min at 150 ? j 0.3 0.4 - mohm no.30 v reg over voltage high v reg_ovh ? warning on icom 14.2 - 16.5 v no.31 v reg over voltage low v reg_ovl ? icom released 13.5 - 15.8 v no.32 v reg over voltage hysteresis v reg_ovhy 0.65 - 1.5 v no.33 v reg under voltage high v reg_uvh ? icom released 7.2 - 8.1 v no.34 v reg under voltage low v reg_uvl ? warning on icom 6.9 - 7.8 v no.35 v reg under voltage hysteresis v reg_uvhy 0.3 - 0.7 v digital supply vdd no.36 v dd operating current i dd ? incl. icom current sourcing 4 - 7 ma no.37 v dd pull down resistance v dd_rpd 200 300 370 kohm no.38 v dd input voltage v dd ? v dd = 3.3v or 5v 3 - 5.5 v no.39 v dd under voltage high v dd_uvh ? icom released 2.55 - 2.95 v no.40 v dd under voltage low v dd_uvl ? warning on icom 2.45 - 2.85 v no.41 v dd under voltage hysteresis v dd_uvhy 0.08 0.10 0.14 v no.42 v dd sleep voltage high v dd_sleeph ? out of sleep 2.1 - 2.7 v no.43 v dd sleep voltage low v dd_sleepl ? go to sleep 1.6 - 2.1 v no.44 v dd sleep voltage hysteresis v dd_sleephy 0.45 0.58 0.80 v
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 11 of 42 r evision 5. 1 C december 1 3 , 2016 gate drivers no.45 rise time t r ? c load = 1nf, 20% to 80% 6 7 15 ns no.46 fall time t f ? c load = 1nf, 80% to 20% 4 7 15 ns no.47 pull - up on resistance low - side pre - driver r on_up ? v sup > 7v ? - 10ma, t j = - 40 ? ? - 10ma, t j = 150 ? ? (for mlx83202) 2.4 (10) - 7.0 (30) ohm pull - up on resistance high - side pre - driver 2.0 (15) - 9.2 (30) ohm no.48 pull - down on resistance low - side pre - driver r on_dn ? v sup > 7v ? 10ma, t j = - 40 ? ? 10ma, t j = 150 ? ? (for mlx83202) 1.5 (10) - 5.7 (30) ohm pull - down on resistance high - side pre - driver 2.0 (15) - 9.2 (30) ohm no.49 turn - on gate drive peak current (sourcing) i gon ? v gs = 0v, v sup > 7v ? (for mlx83202) - - 1.4 ( - 0.45) a no.50 turn - off gate drive peak current (sinking) i goff ? v gs = 12v, v sup > 7v ? (for mlx83202) - 1.6 ( 0.45) a no.51 propagation delay t pddrv ? from logic input threshold to 2v v gs drive output at no load 20 - 120 1 ns no.52 propagation delay matching t pddrvm ? transitions at the different phases at no load condition - 20 - 20 ns no.53 programmable dead time : asynchronous internal delay between high - side and low - side pre - driver of one half bridge t dead ? dead_time [ 2:0] = 000 001 010 011 100 101 110 111 - 25% 0.00 0.51 0.80 1.10 1.67 2.30 3.40 6.90 +25% s no.54 dead time matching between different channels t dead_tol - 15 - 15 % 1 for bare it is specified to 200ns max due measurement accuracy at wafer level
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 12 of 42 r evision 5. 1 C december 1 3 , 2016 no.55 programmable drain - source voltage for monitoring of external n - fets v vds_mon ? vdsmon[2:0] = 000 001 010 011 100 101 110 111 0.40 0.60 0.85 1.05 1.25 1.50 1.70 disabled 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0.60 0.90 1.15 1.45 1.75 2.00 2.30 v no.56 programmable drain - source monitor blanking time: delay between gate high and enabling corresponding v ds monitor t vds_bl vds_blank_time[1:0] = 00 01 10 11 0.60 1.28 2.55 5.10 0.80 1.70 3.40 6.80 1.00 2.13 4.25 8.50 s no.57 sleep gate discharge resistor rsgd ? internal resistance between fet gate - source pins to switch - off fet. v dd = 0v (sleep mode) ? v gs = 0.5v - - 1 kohm no.58 trickle charge pump current capability i tcp ? v sup > 12v ? phasex = v sup ? cpx = phasex + 6.5v ? i tcp,max @150c t j ? i tcp,min @ - 40c t j - 160 - - 25 a no.59 v gs under voltage threshold high v gs_uvh ? icom released 42 - 70 %v reg no.60 v gs under voltage threshold low v gs_uvl ? warning on icom 36 - 63 %v reg no.61 pwm frequency f dr_pwm - 20 100 khz no.62 leakage from cpx - phasex r cp_leak ? r typ at room temperature ? r min at 150 ? j 0.5 1 - mohm no.63 v cpx discharge current i boost_dis ? activated by v sup_ovh event ? from v cpx to v phasex 8 - 40 ma logic ios - fet inputs no.64 digital input high voltage v in_dig_h ? min. voltage logical high 80 - - %v dd no.65 digital input low voltage v in_dig_l ? max. voltage logical low - - 20 %v dd no.66 input pull - up resistance r in_dig_pu ? fetbx 90 - 410 kohm no.67 input pull - down resistance r in_dig_pd ? fettx 90 - 410 kohm
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 13 of 42 r evision 5. 1 C december 1 3 , 2016 logic ios - en input no.68 input pull - down resistance r _en_pd ? en 90 - 410 kohm no.69 bridge disable propagation delay en pr_del ? from bridge disable en<0.2v dd to v gs < 0.5v, c load = 1nf - - 1 s logic ios - icom no.70 pull - up current icom pu ? v icom = 0v - 2.2 - - 5.0 ma no.71 pull - down current icom pd ? v icom = v dd 5.0 - 2.6 ma no.72 icom pwm frequency fast f icomf 85 100 115 khz no.73 icom pwm frequency slow f icoms 10.6 12.5 14.4 khz no.74 spi start - up pulse duration on icom to enter spi mode t spi_su ? en = low ? fettx = low, fetbx = high 2048 / f osc - 4096 / f osc s spi timing no.75 spi initial setup time t spi_isu 2 - - s no.76 spi clock frequency f spi - - 500 khz no.77 rise/fall times t spi_rf ? clk, csb, miso, mosi - - 200 ns no.78 csb setup time t csb_su 1 - - s no.79 csb high time t csb_h 2 - - s no.80 clock high time t clk_h 1 - - s no.81 clock low time t clk_l 1 - - s no.82 data in setup time t di_su 1 - - s no.83 data in hold time t di_h 500 - ns no.84 data out ready delay t do_r ? c load at fetb1 < 50pf - 500 - ns no.85 eeprom read delay t ee_rd ? ee_rd = 1 6 - s no.86 eeprom write delay t ee_wr ? ee_wr = 1 12 - - ms no.87 temperature for eeprom read t j_ee_rd ? junction temperature - 40 - 150 ? temperature for eeprom write t j_ee_wr ? junction temperature - 40 - 150 ?
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 14 of 42 r evision 5. 1 C december 1 3 , 2016 current sense amplifier no.89 input offset voltage v is_io ? input differential voltage within 100mv common mode [ - 0.5, 1.0] v - 7.6 - 7.6 mv no.90 input offset voltage thermal drift v is_io_tdrift - 10 - 10 v/ ? input common mode rejection ratio dc is cmrr_dc 60 - - db no.92 input common mode rejection ratio 1mhz is cmrr_ac 40 - - db no.93 input power supply rejection ratio dc for v dd supply is psrr_dc 60 - - db no.94 input power supply rejection ratio 1mhz for v dd supply is psrr_ac 40 - - db no.95 closed loop gain is gain ? current sense gain = 000 001 010 011 100 101 110 111 - 3% 8.0 10.3 13.3 17.2 22.2 28.7 37.0 47.8 +3% no.96 output settling time is set ? amplified output to 99% of final value after input change - - 1.0 s no.97 output voltage range high v isense_max ? isense output max level v dd - 0.02 - v dd v no.98 output voltage range low v isense_min ? isense output min level gnd - gnd+0.0 2 v no.99 output short circuit current to ground i isense_sc ? output current saturation level - 1.4 - ma no.100 gain bandwidth (gbw) is gbw 6 - - mhz no.101 output slew rate is sr -- 8 - v/s no.102 cm spike recovery is cm_rec ? cm spike = 1.5v, t=250ns - - 730 ns no.103 vref voltage input v ref 0 - 50 %v dd table 10 - 1 general electrical specifications
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 15 of 42 r evision 5. 1 C december 1 3 , 2016 10.1. mlx83203 typical performance graphs figure 10 - 1 mlx83203 regulated output voltage vs. supply voltage figure 10 - 2 mlx83203 regulated output voltage vs. supply voltage figure 10 - 3 mlx83203 high - side driver fet r on resistance vs. supply voltage figure 10 - 4 mlx83203 high - side driver fet r off resistance vs. supply voltage figure 10 - 5 mlx83203 low - side driver fet r on resistance vs. supply voltage figure 10 - 6 mlx83203 low - side driver fet r off resistance vs. supply voltage
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 16 of 42 r evision 5. 1 C december 1 3 , 2016 10.2. mlx83202 typical performance graphs figure 10 - 7 mlx83202 regulated output voltage vs. supply voltage figure 10 - 8 mlx83202 regulated output voltage vs. supply voltage figure 10 - 9 mlx83202 high - side driver fet r on resistance vs. supply voltage figure 10 - 10 mlx83202 high - side driver fet r off resistance vs. supply voltage figure 10 - 11 mlx8320 2 low - side driver fet r on resistance vs. supply voltage figure 10 - 12 mlx83202 low - side driver fet r off resistance vs. supply voltage
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 17 of 42 r evision 5. 1 C december 1 3 , 2016 11. block diagram figure 11 - 1 block diagram b i - d i r e c t i o n a l , s e r i a l d i a g n o s t i c s i n t e r f a c e i c o m _ o u t i c o m _ i n g a t e d r i v e r l o g i c e r r o r c o n t r o l l e r c u r r e n t s e n s e a m p l i f i e r g a i n 1 d r i v e r s t a g e t r i c k l e c h a r g e p u m p t o p d r i v e r b o t t o m d r i v e r 3 x v d d v d d d e a d t i m e d e a d t i m e e e p r o m c u s t o m s p i i n t e r f a c e c h a r g e p u m p c h a r g e p u m p c o n t r o l c o m p c h a r g e p u m p m o d e v s u p 3 . 3 v r c o p o r b a n d g a p 1 2 v r e g u l a t o r s u p p l y m o n i t o r v d d v d d _ u v v s u p _ o v v s u p _ u v v b o o s t _ u v v r e g _ o v v r e g _ u v v s u p v b o o s t v s u p v r e g v r e g e x t e r n a l f e t m o n i t o r i n g v b a t f p h a s e x g a t e t x p h a s e x 3 x h s v d s _ o v 3 x h s v g s _ u v p h a s e x i b p 3 x l s v d s _ o v e e p r o m e r r t e m p e r a t u r e o v t w a r n i n g f e t t x e n f e t b x i c o m v d d v s u p c p v b o o s t v r e g v b a t f c p x g a t e t x p h a s e x g a t e b x i b p i b m i s e n s e v r e f a g n d d g n d v d d 3 x 3 3 v b a t
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 18 of 42 r evision 5. 1 C december 1 3 , 2016 12. functional description 12.1. supply system the mlx83203 - 2 is supplied via pins vsup and vdd. the power supply vsup supplies the internal operation of the pre - driver, the charge pump and the voltage regulator used for the bootstrap based architecture. the digital supply vdd supplies the ios and the cur rent sense amplifier. figure 12 - 1 principle o rganization of the supply s ystem 12.1.1. power supply - vsup the internal operation of the pre - driver is supplied from the power supply input pin vsup. it supplies the bandgap reference, power - on - reset system and internal 3.3v regulator. this 3.3v regulator in turn supplies the eeprom, rc - oscillator and diagnostics. for safety reasons the pre - driver provides integrated under volta ge and over voltage detection on vsup . 12.1.2. charge pump - vboost the ic comprises a charge pump, supplied from vsup, which allows full device operation down to 4.5v. the charge pump boosted output voltage is available on vboost. this boosted voltage powers the voltage regulator vreg used to supply the low - side drivers d irectly, and high - side drivers via the bootstrap architecture. see error! reference source not found. figure 4 - 1 for the standard charge pump configuration here vboost is regulated relative to ground. the charge pump will not be switching when v sup > v reg + 2xv f, diode . an alternative mode of operati on for the charge pump supports the use of an external low drop n - fet for reverse polarity protection. in this mode the charge pump boosts the output voltage relative to the supply voltage instead of relative to ground, see application diagram in figure 4 - 2 . the disadvantage is an additional amount of dissipation inside the driver to regulate vreg. the charge pump architecture is a supply voltage doubler with feedback loop for stable output voltage generation, as shown in figure 12 - 2 . it can be co nfigured in eeprom to either regulate the boosted output voltage vboost relative to ground or relative to the supply voltage, see figure 12 - 3 for the t ypical output voltage. furthermore the eeprom configuration allows disabling the charge pump for applications not requiring the low voltage operation, in order to reduce the overall power consumption. v s u p 3 . 3 v v b g p o r v d d i o s c s a r c o e e p r o m d i a g n o s t i c s v r e g d r i v e r s i n p u t s o u t p u t s i n t e r n a l v b o o s t c p
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 19 of 42 r evision 5. 1 C december 1 3 , 2016 for safety reasons the pre - driver provides integrated under voltage detection on vboost. in addition the charge pump comprises a discharge switch in order to keep vboost output voltage in a safe operating area in case of over voltage on the supply input pin. the disch arge switch is activated as soon as the supply voltage vsup exceeds the v sup_ovh threshold level and is deactivated when it drops below the v sup_ovl threshold. at the same time the charge pump is deactivated. en_cp cpmode charge pump configuration 0 x charge pump disabled 1 0 charge pump configured to regulate vboost relative to ground, to support low voltage operation 1 1 charge pump configured to regulate vboost relative to the supply, to support the use of a reverse polarity n - fet table 12 - 1 charge p ump c onfiguration o ptions figure 12 - 2 charge pump principle s chematic c o n t r o l l e v e l s h i f t w i t h d e a d t i m e & s l o p e c o m p c o m p o p a e n _ c p c p _ f b v b o o s t _ u v c p m o d e v s u p v s u p c p _ d s c h g v s u p c p v b o o s t f c p c p m o d e
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 20 of 42 r evision 5. 1 C december 1 3 , 2016 figure 12 - 3 charge p ump output and driver s upply 12.1.3. voltage regulator - vreg the voltage regulator regulates the power supply down to 12v, in order to supply the low - side gate drivers and switch the external low - side n - fets without gate - source over voltage at high battery voltages. the regulat ed output voltage vreg further provides the bootstrap voltage for driving the high - side n - fets. for safety reasons the pre - driver provides integrated under voltage and over vo ltage detection on vreg. 0 v 3 v 5 v 8 v 10 v 13 v 15 v 18 v 20 v 23 v 25 v 4.0 v 6.0 v 8.0 v 10.0 v 12.0 v voltage [v] v sup [v] charge pump and voltage regulator output vs power supply input cp mode 0 - vboost cp mode 1 - vboost vreg cpx-gatetx
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 21 of 42 r evision 5. 1 C december 1 3 , 2016 figure 12 - 4 voltage r egulator for d river s upply C vreg 12.1.4. digital supply - vdd the mlx83203 - 2 comprises a current sense amplifier. the current sense amplifier and ios are supplied from the digital supply vdd. for safety reasons the pre - driver provides integrated under voltage detection on vd d. note: when supplying vdd with a limited output impedance (e.g. from a microcontroller io) the performance of the amplifier may be affected. 12.1.5. sleep mode sleep mode is activated when the digital supply input vdd is pulled below vvdd sleep voltage threshold low . in sleep mode the charge pump is disabled and the current consumption on vsup is reduced. all gate drivers are switched off via sleep gate discharge resistors r sgd . t he pre - driver will wake - up as soon as the voltage level on vdd rises above vvdd sleep voltage threshold high . t o p d r v b o t d r v c p x g a t e t x p h a s e x g a t e b x t o p d r v b o t d r v t o p d r i v e r b o t t o m d r i v e r c c p x r s h u n t 1 2 v r e g u l a t o r v r e g 3 3 3 3 t o p d r v t o p d r v t r i c k l e c h a r g e p u m p v b a t f
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 22 of 42 r evision 5. 1 C december 1 3 , 2016 pin name state in sleep mode cp the charge pump is disabled. vboost since the charge pump is disabled vboost is pulled to the supply voltage via the external charge pump diodes. gatebx in sleep mode, gate - discharge resistors (r sgd ) between gatebx and dgnd are activated, ensuring all low - side gate drivers are switched off gatetx in sleep mode, gate - discharge resistors (r sgd ) between gatetx and phasex are activated, ensuring all high - side gate drivers are switched off phasex phases are kept low with gatetx through the internal body diode of the pre - driver vreg voltage regulator is disabled cpx any charge that remains after vreg is disabled will leak to ground isense current sense amplifier is supplied from vdd, and thus not active fetbx, fettx en, icom all ios are supplied from vdd, and thus not active table 12 - 2 drivers in sleep mode notes: 1. in case any of the digital input pins are externally pulled high while vdd is low, current will flow into vdd via internal esd protection diodes . this condition is not allowed. 2. when vdd is pulled low, also icom will go low. this should not be interpreted as a diagnostic interrupt. figure 13 - 1 - 5 drivers in sleep mode c p x g a t e t x p h a s e x v r e g g a t e b x r s g d r s g d
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 23 of 42 r evision 5. 1 C december 1 3 , 2016 12.2. gate drivers 12.2.1. pwm input control logic C fetbx & fettx each of the 6 external n - fets can be controlled independently via the 6 digital pwm input pins: fetbx and fettx. however, the digital logic provides the option to control the 3 external half bridges with only 3 control signals, by shorting high - side and lo w - side pwm input pins for each half bridge. the ic provides internal shoot through protection since the digital logic prevent s simultaneous activation of both high - side and low - side driver of one half bridge. a configurable dead time ensure s the high - side (low - side) n - fet is fully switched off, before switching on the complementary low - side (high - side) n - fet. for safety reasons the pre - driver provides integrate d drain - source and gate - source monitoring for each of the 6 external n - fets. figure 12 - 5 input c ontrol l ogic of the d river s tage 12.2.2. enable input en the enable input pin en enables the gate driver outputs when set high. when reset, all gate driver outputs are switched to the low state, switching off all external n - fets. this is performed by pulling all gate drivers to ground via the pull - down on - resist ances . the enable pin can be used by the microcontroller to disable all drivers in case of any fault detection. while en is low, the programming of the eeprom via spi can be initiated by pulling icom low for the spi start - up time specified by t spi_su . 12.2.3. gate driver supply and bootstrap architecture C vreg & cpx the voltage regulator regulates the power supply voltage down to 12v. the regulated voltage is used to directly supply the low - si de drivers. to provide sufficient supply voltage for the high - side drivers a bootstrap architecture is used. when the low - side n - fet is switched on, the phase voltage will be pulled low and the bootstrap capacitor is charged from the vreg buffer capacitor through the bootstrap diode. afterwards, if the low - side n - fet is switched off and the high - side n - fet is switched on, the charge of the bootstrap capacitor is used to supply sufficient gate drive voltage to the high - side n - fet. the integrated trickle char ge pump assures the bootstrap capacitor will not be discharged, and allows 100% pwm operation. g a t e t x p h a s e x g a t e b x d e a d t i m e d e a d t i m e f e t t x f e t b x e n
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 24 of 42 r evision 5. 1 C december 1 3 , 2016 12.3. integrated current sense amplifier the ic comprises an integrated fast, high - bandwidth, low offset current sense amplifier. the current sense amplifier is suppl ied from the digital supply. it senses the voltage over the low - side shunt, amplifies it with the gain programmed in eeprom and adds the offset provided on vref. the output of the amplifier is available on isense. figure 12 - 6 current sense amplifier v d d v r e f i b p i b m i s e n s e o p a o p a 1
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 25 of 42 r evision 5. 1 C december 1 3 , 2016 12.4. protection and diagnostic functions 12.4.1. power supply over voltage shutdown (vsup_ov) the pre - driver has an integrated vsup over voltage shut down to prevent destruction of the ic at high supply voltages. 12.4.2. power supply under voltage warning (vsup_uv) the pre - driver has an integrated vsup under voltage detection . the diagnostics interface will give a warning to the microcontroller. it is the responsibility of the microcontroller to take action in order to ensure reliable operation. 12.4.3. digital supply under voltage warning ( vdd_uv) the pre - driver has an integrated vdd under voltage detection . the diagnostics interface will give a warning to the microcontroller. it is the responsibility of the microcontroller to take action in order to e nsure reliable communication between microcontroller and pre - driver. 12.4.4. vboost under voltage warning (vboost_uv) the integrated charge pump boosts the supply voltage in low voltage operation on the vboost output. there is an under voltage detection on vboost to warn the microcontroller the charge pump is not ready. it is the responsibility of the microcontroller to take action in order to ensure reliable motor operation. 12.4.5. gate driver supply over voltage warning/shutdown (vreg _ov) the mlx83203 - 2 comprises an integrated vreg over voltage detection . the reaction of the pre - driver on this vreg_ov event depends on the status of the bridge feedback bit in eeprom. if this vreg_ov_bf_en bit is set the pre - driver will disable all gate drivers, switching off all external n - fets. if the bit is reset it will just give a warning to the microcontroller. vreg_ov_bf_en pre - driver reaction vreg_ov event 0 vreg_ov is reported on icom, but the drivers remain active 1 vreg_ov is reported on icom and the drivers are disabled table 12 - 3 eeprom configuration for vreg over voltage d etection 12.4.6. gate driver supply under voltage warning (vreg_uv) the pre - driver detects when the regulated voltage drops below the under voltage threshold . the diagnostics interface will give a warning to the microcontroller. it is the responsibility of the micro controller to take action in order to ensure reliable switching of the external n - fets, since the vreg voltage directly supplies the low - side gate drivers.
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 26 of 42 r evision 5. 1 C december 1 3 , 2016 12.4.7. gate source voltage monitoring warning (vgs_uv) in order to ensure reliable switching of the high - si de n - fets, the mlx83203 - 2 comprises gate - source monitors for each of the high - side n - fets. in case of an under voltage , the diagnostics interface will give a warning to the microcontroller, if the gate - source comparators are enabled in eeprom . it is the responsibility of the microcontroller to take action in order to ensure reliable switching of the high - side gate drivers. 12.4.8. over temperature warning (ovt) if the junction temperature exceeds th e specified threshold , a warning will be communicated to the microcontroller. the pre - driver will continue in normal operation. it is the responsibility of the microcontroller to protect the ic against over temperatu re destruction. 12.4.9. shoot through protection and dead time the pre - drivers internal implementation guarantees that low - side and high - side n - fet of the same external half bridge cannot be conducting at the same time, preve nting a short between the supply and ground. in addition the pre - driver provides a programmable dead time in eeprom. the dead time sets the delay between the moment when the high - side (low - side) n - fet is switched off, and the moment when the complementary low - side (high - side) n - fet can be switched on. 12.4.10. drain - source voltage monitoring warning/shutdown (vds_err) the mlx83203 - 2 provides a drain - source voltage monitoring feature for each exter nal n - fet to protect against short circuits to ground or supply. for the high - sides the drain - source voltage are sensed via the vbatf C and phasex - pins. for the low - sides the phasex C and ibp - pins are used. the drain - source vol tage comparator can be enabled or disabled in eeprom. the drain - source voltage monitor for a certain external n - fet is activated when the corresponding input is switched on and the dead time has passed. an additional blan king time can be programmed in eeprom. if the drain - source voltage remains higher than the vds monitor threshold voltage , the vds error is raised. the threshold voltage is configurable in eeprom. the reaction of the pre - driver on a vds error can be configured in eeprom with the bridge feedback bit. if this bit is set the pre - driver automatically disables the drivers when a vds error is detected. if the bit is reset, t he drivers remain active. in both cases the vds error will be reported to the microcontroller. vds_comp_en vds_bf_en pre - driver reaction on vds - error event 0 x any vds error is ignored and no error is reported on icom 1 0 vds_err is reported on icom, but the drivers remain active 1 1 vds_err is reported on icom and the drivers are disabled table 12 - 4 eeprom configuration for d rain - s ource e rror d etection
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 27 of 42 r evision 5. 1 C december 1 3 , 2016 12.4.11. eeprom error warning (eep_err) to ensure reliable communication with eeprom the pre - driver provides an automatic single bit error correction and double error detection. if two bits in the addressed word are bad the eeprom gives the eep_err warning, indicating a double error was detected. 12.4.12. diagnostics inter face C icom all diagnostic events described above are reported to the microcontroller via a single pin, icom. in normal operation, when no error is detected, icom is default high. the icom interface acts as a serial interface that feeds back detailed diag nostics information. if an error is detected, icom goes from default high to communicating a pwm - signal . the speed of this pwm signal depends on the eeprom configuration of bit pwm_speed . each error corresponds to a duty cycle with a 5 - bit resolution. thus the microcontroller can distinguish different errors by reading the duty cycle, see table 12 - 7 . pwm_speed description 0 slow mode: for slow microcontrollers 1 fast mode : for fastest response of microcontroller table 12 - 5 eeprom configuration for diagnostics c ommunication speed the duty cycle is transmitted until the microcontroller sends the acknowledgement. this is done by pulling icom low for more than a pwm - period , t ack > t icom . at each icom falling edge the pre - driver checks the actual voltage on icom in order to detect an acknowledgement. after acknowledgement the duty cycle of the next error is transmitted, if multiple errors were detected. all errors have been reported when the end - of - frame duty cycle is send. when all errors are physically removed, and the end - of - frame message is acknowledged by the microcontroller, icom returns to its default high state. figure 12 - 7 icom diagnostics communication p h y s i c a l e r r o r i c o m m c u a c k n o w l e d g e e r r o r i n f o r m a t i o n e n d - o f - f r a m e d e f a u l t h i g h d e f a u l t h i g h
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 28 of 42 r evision 5. 1 C december 1 3 , 2016 notes: 1. when vdd is pulled low to put the pre - driver in sleep mode, icom will go low as well. this should not be interpreted as a diagnostic interrupt. as soon as vdd goes high, the pre - driver wakes - up and icom will return to its default high state. 2. at por it is possible that the voltages on vsup and vreg were not above the under voltage thresholds (e.g. due to charging of external capacitors). it is possible that icom reports these under voltage errors after por. this implies that the microcontroller has to acknowledge these errors before icom wil l be in its default high state and the pre - driver is ready for normal operation. the drivers are disabled when the drivers are enabled again as soon as an error condition is detected for which the h ardware protection is activated vsup_ov vreg_ov vds_err the microcontroller acknowledges the error vdd = low (sleep mode) vdd = high (wake - up) en = low en = high table 12 - 6 pre - driver output state summary figure 12 - 8 icom diagnostics interface in case multiple errors occur at the same time, the priority is as defined in table 12 - 7 . the highest priority is 0 and 16 is the lowest priority. m i c r o c o n t r o l l e r p r e - d r i v e r c l o a d < 1 0 0 p f v d d < 5 m a < 5 m a i n t e r r u p t / r e a d d u t y c y c l e a c k n o w l e d g e i c o m v d d i c o m _ o u t i c o m _ i n
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 29 of 42 r evision 5. 1 C december 1 3 , 2016 priority error event % duty cycle debounce time description 11 icom_eof 93.5 n/a end of frame 10 vds_err 82.5 2 s vds error = vds_t1 | vds_t2 | vds_t3 | vds_b1 | vds_b2 | vds_b3 this event can be masked by setting vds_comp_en = 0 to avoid erroneous triggering due to switching there is a programmable blanking time on top of the debounce time: vds_blank_time[1:0]. 9 eep_err 55.0 n/a eeprom dual error detected 8 vdd_uv 49.5 8 s vdd under voltage 7 vsup_ov 44.0 2 s vsup over voltage 6 vsup_uv 38.5 8 s vsup under voltage 5 ovt 33.0 2 s ovt over temperature 4 vreg_uv 27.5 16 s vreg under voltage 3 vgs_uv 22.0 2 s vgs under voltage this event can be masked by setting vgs_uv_comp_en = 0 2 vboost_uv 16.5 16 s vboost under voltage 1 vreg_ov 11.0 2 s vreg over voltage this event can be masked by setting vgs_uv_comp_en = 0 table 12 - 7 overview diagnostics over icom with priority definitions
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 30 of 42 r evision 5. 1 C december 1 3 , 2016 12.5. eeprom configuration the mlx83203 - 2 provides an eeprom for configuration of the ic, the current sense amplifier and over current comparator, protection and diagnosti c functions. this allows to optimize the pre - drivers operation for the application requirements. the configuration can be done at customer production testing by using the ptc - 04, or by the microcontroller via a custom program interface. the eeprom feature s single error correction and double error detection . 12.5.1. memory map the mlx83203 - 2 comprises 6 bytes of eeprom for user configurability. the first two bytes are not used for the internal configuration of the pre - driver, and can thus be used by the customer for traceability purposes. the other 4 bytes are used for configura tion of the current sense amplifier and configuration of the diagnostics. the pre - driver is programmed with default settings per table below. address ed7 ed6 ed5 ed4 ed3 ed2 ed1 ed0 0 - - - - - - - res. 0x00 0 0 0 0 0 0 0 0 1 - - - - - - - res. 0x00 0 0 0 0 0 0 0 0 2 dead_time[2:0] vdsmon[2:0] cpmode res. 0x7c 011 111 0 0 3 vds_blank_time[1:0] pwm_speed - cur_gain[2:0] res. 0x86 10 0 0 011 0 4 vreg_ov _bf_en vds _bf_en vds _comp_en vgs_uv _comp_en en_tcp en_cp - res. 0xf4 1 1 1 1 0 1 0 0 5( - 6 - 7) spi_en res. - - - - - res. 0xc0 1 1 0 0 0 0 0 0 table 12 - 8 eeprom memory map and default configuration
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 31 of 42 r evision 5. 1 C december 1 3 , 2016 bit name description default configuration of the ic cpmode defines the mode of operation of the internal charge pump 1: vboost voltage is regulated relative to vsup for reverse polarity n - fet protection 0: vboost voltage is regulated relative to gnd for low voltage operation with minimal power consumption 0 en_cp defines the status of the pre - drivers internal charge pump drivers trickle charge pump drivers reaction on a regulated supply over voltage: ivers drain drivers reaction on a drain drivers gate table 12 - 9 eeprom bit description
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 32 of 42 r evision 5. 1 C december 1 3 , 2016 12.5.2. spi program mode the eeprom memory can be accessed through a custom spi interface. it allows the user to read/program the eeprom by the microcontroller in the application. this custom interface re - uses the low - side driver pins for spi communication. since the same pins ar e used for both reading/writing the eeprom and for controlling the motor, the eeprom is only accessible when the motor is not running. furthermore it is necessary to apply a certain sequence of conditions before the pre - driver will enter the spi program m ode. once in this mode, the eeprom can be accessed for reading and writing, until the ic enters normal mode again and motor operation is possible. figure 12 - 9 custom s pi i nterface pin name spi signal description icom csb spi - frames are defined by csb low fetb3 mosi the mosi (master out C C table 12 - 10 spi signals entering spi program mode 12.5.2.1. the mlx83203 - 2 e nter s spi program mode when all below conditions are satisfied: ? en = 0 ? fettx = low (high - side fet inputs off) ? fetbx = high (low - side fet inputs off) ? icom ? any pending errors have been removed and acknowledged, so icom is in default high state ? a low level pulse is applied on icom for a time t spi_su . d r i v e r l o g i c c u s t o m s p i e e p r o m d i a g n o s t i c s e n f e t t x f e t b x i c o m
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 33 of 42 r evision 5. 1 C december 1 3 , 2016 exiting spi program mode 12.5.2.2. the mlx83203 - 2 will exit the spi program mode when the enable input en is pulled high. similar to when the mlx83203 - 2 comes out of por, after leaving the spi program mode the pre - driver is blocked until the data have been copied to the registers. meaning that before entering normal mode the eeprom write will be completed and the eeprom state machine will copy all eeprom contents into r egisters. during this time icom is kept low. when it returns to its default high state the pre - driver is ready for normal operation. protocol 12.5.2.3. once the ic is in spi program mode the microcontroller can read/write the eeprom, following the protocol depicte d below. figure 12 - 10 spi protocol (lsb first) registers description 12.5.2.4. mosi [15:0] bit [15] bit [14] bit [13] bit [12] bit [11] bit [10] bit [9] bit [8] mosi_par x x cmd [1:0] mosi_data [7:5] bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] mosi_data [4:1] x address [2:0] table 12 - 11 mosi f rame d escription miso[15:0] bit [15] bit [14] bit [13] bit [12] bit [11] bit [10] bit [9] bit [8] miso_par comm_err ee_ready cmd [1:0] miso_data [7:5] bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] miso_data [4:1] x address [2:0] table 12 - 12 miso frame d escription n + 2 [ 0 ] n + 2 [ 1 ] c s b c l k m o s i m i s o l a t c h d a t a i n t o m o s i r e g i s t e r o n c l k r i s i n g e d g e n [ 0 ] r e a d i n s t r u c t i o n i f c o m m _ e r r = 0 s t a r t e e _ r d e e _ r e a d y = 1 d a t a i n d a t a l a t c h c o p y l a t c h e d d a t a i n t o m i s o [ 1 0 : 4 ] m i s o [ 1 0 : 4 ] c o n t a i n s d a t a r e q u e s t e d i n p r e v i o u s r e a d i n s t r u c t i o n n [ 1 ] n [ 2 ] n [ 0 ] n [ 1 ] n + 1 [ 0 ] n + 1 [ 1 ] n + 1 [ 2 ] n [ 1 ] n [ 1 5 ] n [ 1 5 ] d a t a o n m i s o s t a b l e ( v a l i d ) w h i l e c l k i s l o w w r i t e i n s t r u c t i o n n [ 1 ] n + 1 [ 1 5 ] e e _ r e a d y = 1 d a t a i n d a t a l a t c h r e g i s t e r i f c o m m _ e r r = 0 s t a r t e e _ w r c o p y l a t c h e d d a t a ( n o t r e a d f r o m e e p r o m ! ) i n t o m i s o [ 1 0 : 4 ] m i s o [ 1 0 : 4 ] c o n t a i n s p r e v i o u s m o s i [ 1 0 : 4 ] d a t a n + 1 [ 0 ] n + 1 [ 1 ] n + 1 [ 1 5 ] n + 2 [ 0 ] n + 2 [ 1 ] > t e e _ w r > t e e _ r d
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 34 of 42 r evision 5. 1 C december 1 3 , 2016 bit description address address of the byte in eeprom that needs to be read/written to. mosi_data[7:1] in case of write command, the data that needs to be written. dont care for any read ee_rd and t ee_wr respectively. these times define the minimum time csb (icom) has to remain high between two spi - frames in order to finish the read/ write action. as soon as the read/write action starts, t he ee_ready bit is reset. after completion of the read/write action the bit is set. if the read/write delay between spi - frames was long enough to execute the read/write action, the ee_ready bit will thus be set, signaling the read/write action was finish ed. if the time was too short, the bit will still be 0. comm_err this bit indicates if the previous mosi - frame was received correctly. if no communication error occurred the bit will be reset, and the read/write action was started as soon as csb was pulled high. if a communication error occurred in the previous mosi - frame the read/write command was not executed. possible communication errors are: odd parity bit was set incorrect number of clock periods was not equal to 16 mosi_par, miso_par odd parity bit of the current mosi/miso frame. table 12 - 13 mosi/miso frames bit d escription
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 35 of 42 r evision 5. 1 C december 1 3 , 2016 figure 12 - 11 mosi/miso r egisters and relation to i nternal d ata l atches read instruction 12.5.2.5. in order to read one of the eeprom bytes, the microcontroller should compose the mosi(n) frame according to table 12 - 11 with the address it wants to read, the read command and set the odd parity bit in a correct way. after transmission of this mosi(n) - frame and when the csb signal is pulled high, the pre - driver will start to read the data at the specific address. if csb is kept high long enough for the pre - driver to execute the read action, it will transmit the read data on the next miso(n+1) - frame. the data in this miso(n+1) - frame is valid only if ? co mm_err = 0 : no communication error was detected on the previous mosi(n) - frame ? ee_ready = 1 : the read delay was long enough to finish the read ? miso_par = correct : the miso(n+1) - frame has a correct odd parity bit l a t c h e s m i s o c m d [ 1 : 0 ] m o s i _ d a t a [ 6 : 0 ] m o s i _ p a r x x x a d d r e s s [ 2 : 0 ] c m d [ 1 : 0 ] m i s o _ d a t a [ 6 : 0 ] m i s o _ p a r e e _ r e a d y c o m m _ e r r x a d d r e s s [ 2 : 0 ] [ 1 1 : 1 2 ] [ 1 0 : 4 ] 1 5 1 4 1 3 3 [ 2 : 0 ] e e p r o m c o m m _ e r r c l k c o u n t e r = 1 6 m o s i e e _ r e a d y d a t a [ 6 : 0 ]
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 36 of 42 r evision 5. 1 C december 1 3 , 2016 write instruction 12.5.2.6. the mlx83203 - 2 pro vides different configuration options through the eeprom programming. in order to program one of the eeprom bytes, the microcontroller should compose the mosi(n) frame according to table 12 - 11 with the address and data it wants to write, the write command and set the odd parity bit in a correct way. after transmission of this mosi(n) - frame and when the csb signal is pulled high, the pre - driver will star t to write the data at the specific address. if csb is kept high long enough the pre - driver will be able to complete the write instruction. in total three verification steps are possible in order to ensure successful writing of the eeprom. on the first mis o - frame after the write command, it can be checked if the write command is received correctly and the correct address and data are used. in the next two miso - frames the data written in eeprom can be read in order to guarantee the desired data has been writ ten in eeprom ? verification step 1: correct receive of the write instruction using the miso(n+1) - frame ? comm_err = 0 : no communication error detected on mosi(n) - write command ? ee_ready = 1 : the write delay was long enough to finish the write instruction ? m iso_par = correct : the miso(n+1) - frame has a correct odd parity bit ? miso_data(n+1) = mosi_data(n) : the correct data was used for the write instruction ? verification step2: ee_rdaw1 using the miso(n+2) - frame ? comm_err = 0 : no communication error detect ed on mosi(n+2) - rdaw1 command ? ee_ready = 1 : the read delay was long enough to finish the read instruction ? miso_par = correct : the miso(n+2) - frame has a correct odd parity bit ? miso_data(n+2) = mosi_data(n) : the correct data is written ? verification st ep3: ee_rdaw2 using the miso(n+3) - frame ? comm_err = 0 : no communication error detected on mosi(n+3) - rdaw2 command ? ee_ready = 1 : the read delay was long enough to finish the read instruction ? miso_par = correct : the miso(n+3) - frame has a correct odd parity bit ? miso_data(n+3) = mosi_data(n) : the correct data is written
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 37 of 42 r evision 5. 1 C december 1 3 , 2016 13. esd protection figure 1 3 - 1 principle schematic highlighting esd connections note: all pins are referenced to the driver ground dgnd as depicted in the picture above, but only for the esd protection. c u r r e n t s e n s e a m p l i f i e r e s d c o n n e c t i o n s d i g i t a l i o e s d c o n n e c t i o n s g a t e d r i v e r e s d c o n n e c t i o n s s u p p l y e s d c o n n e c t i o n s v b a t f v s u p d g n d c p d g n d v r e g d g n d 1 8 . 5 v v d d d g n d 8 v a g n d d g n d c p x g a t e t x p h a s e x d g n d d g n d 5 5 v 1 8 . 5 v v r e g g a t e b x d g n d v d d f e t b x d g n d v d d f e t t x v d d i c o m e n d g n d d g n d d g n d i b p d g n d i b m v d d o p a v d d d g n d i s e n s e 1 8 . 5 v 5 5 v v b o o s t d g n d 5 5 v v d d v r e f d g n d d g n d 9 v o c i n 1 0 v
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 38 of 42 r evision 5. 1 C december 1 3 , 2016 14. package information 14.1. package marking product name: mlx83203 - 2 lot number: zzzzzzzz format free date code: yyww year and week figure 14 - 1 package marking 14.2. package data figure 14 - 2 package drawing and mechanical dimensions m l x 8 3 2 0 x z z z z z z z z y y w w
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 39 of 42 r evision 5. 1 C december 1 3 , 2016 15. standard information regarding manufacturability of melexis products with different soldering processes our products are classified and qualified regarding soldering technology, solderability and moisture sensitivity level according to following test methods: reflow soldering smds (surface mount devices) ? ipc/jedec j - std - 020 : moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices (classification reflow profiles according to table 5 - 2) ? eia/jedec jesd22 - a113 : preconditioning of nonhermetic surface mount devices prior to reliability testing (reflow profiles according to table 2) wave soldering smds (surface mount devices) and thds (through hole devices) ? en60749 - 20 : resistance of plastic - encapsulated smds to combined effect of moisture and soldering heat ? eia/jedec jesd22 - b106 and en60749 - 15 : resistance to soldering temperature for through - hole mounted devices iron soldering thds (through hole devices) ? en60749 - 15 : resist a nce to soldering temperature for through - hole mounted devices solderability smds (surface mount devices) and t hds (through hole devices) ? eia/jedec jesd22 - b102 and en60749 - 21 : solderability for all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classif ication and qualification tests have to be agreed upon with melexis. the application of wave soldering for smds is allowed only after consulting melexis regarding assurance of adhesive strength between device and board. melexis recommends reviewing on our web site the general guidelines soldering recommendation ( http://www.melexis.com/quality_soldering.aspx ) as well as trim&form recom mend ations ( http://www.melexis.com/ assets/trim - and - form - recommendations - 5565.aspx ). melexis is contributing to global environmental conservation by promoting lead free so lutions. for more information on qualifications of rohs compliant products (rohs = european directive on the restriction of the use of certain hazardous substances) please visit the quality page on our website: http://www.melexis.com/quality.aspx 16. esd precautions electronic semiconductor products are sensitive to electro static discharge (esd). always observe electro static discharge control procedures whenever handling semiconductor products.
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 40 of 42 r evision 5. 1 C december 1 3 , 2016 17. revision h istory revision date description 1.0 01 - 02 - 12 ? initial draft version 1.1 01 - 03 - 12 ? ee_rd meaning in spi description corrected ? rdson specification split up in on/off ? added rdson for 83202 variant ? added package marking 1.2 28 - 03 - 12 ? tqfp48 pin out included 1.3 15 - 05 - 12 ? added appl. schematics, pin internal structures, updated block diagram ? updated spi enabling. ? updated icom duty cycles ? updated sleep mode ? updated leakage spec on vbatf ? max voltage on all pins 1.4 03 - 07 - 12 ? final package dimensions 1.5 28 - 11 - 12 ? parameters updated per test data ? device description updated 1.6 21 - 12 - 12 ? information about dc variant of pre - driver moved to separate datasheet 1.7 15 - 01 - 13 ? protection and diagnostic functions updated ? trickle charge pump included 2.0 26 - 02 - 13 ? customer release 2.1 06 - 05 - 13 ? max voltage on phase pins updated 2.2 04 - 12 - 13 ? entering spi mode by disabling all 6x fet input signals 2.3 01 - 03 - 14 ? temperature codes for ordering information updated ? abs. max. rating updated ? driver stage specification for 83202 variant added ? block diagram and application diagrams updated ? changed icom duty cycle for vds_err from 5.5% to 82.5% 3.0 09 - 05 - 14 ? general update according to new template 3.1 24 - 07 - 14 ? drain - source monitor blanking ? trickle charge pump current capability ? largest dead time value ? icom pull - up current 4.0 31 - 07 - 14 ? performance graphs added 4.1 02 - 11 - 15 ? tqfp version cancelled 4.2 18 - 12 - 15 ? electrical specifications updated ? operating current from v sup (with pwm operation) ? vsup under and over voltage hysteresis
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 41 of 42 r evision 5. 1 C december 1 3 , 2016 ? internal leakage from v batf to gnd ? v dd operating current ? drivers resistance for mlx83202 ? discharge currents for v boost and v cpx specified in case of v sup_ovh ? ordering information is updated ? packa ge information updated 4.3 17 - 03 - 16 ? data in hold time and data out ready delay units corrected to ns 4.4 31 - 08 - 16 ? default eeprom configuration corrected for pwm_speed & en_tcp ? minimum specification on input pwm frequency removed ? drain - source voltage monitoring description updated with pin - description 5.0 01 - 09 - 16 ? new melexis template 5.1 1 3 - 1 2 - 16 ? no reduced gate drive voltage for higher extended supply range table 17 - 1 revision history
mlx83203 - mlx83202 automotive 3 - phase bldc pre - driver datasheet page 42 of 42 r evision 5. 1 C december 1 3 , 2016 18. disclaimer devices sold by melexis are covered by the warranty and patent indemnification provisions appearing in its term of sale. melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. melexis reserves the right to change specifications and p rices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with melexis for current information. this product is intended for use in normal commercial applications. applications requiring extend ed temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life - support or life - sustaining equipment are specifically not recommended without additional processing by melexis for each application. the information furnished by melexis is believed to be correct and accurate. however, melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party sh all arise or flow out of melexis rendering of technical or other services. ? 2016 melexis nv. all rights reserved. www.melexis.com

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